Prof. Nael Abu-Ghazaleh and his research team have designed a novel, patent-pending architecture for register coalescing to improve performance and energy efficiency – called CORF. Register coalescing combines multiple registers reads into a single physical register read. The proposed design takes advantage of the coalescing opportunities through a combination of compiler-guided register allocation and coalescing-aware register organization. To maximize operand coalescing opportunities, CORF combines compiler-assisted register allocation with a reorganized RF – called CORF++.
CORF++ Overview. At compile time, the alignment of the register through graph coloring algorithm to maximize coalescing opportunities.
The benefits of their invention are:
- Allows multiple operands to be read in a single cycle, overcoming port serialization.
- The pressure on the RF is reduced potentially reducing register bank conflicts.
- Combined savings of 17% in dynamic energy, reduction in number of reads by 23%, improvement in instruction per cycle/computation by 9%, and 52% of the leakage energy.
|Technique||IPC||Register reads||RF Dynamic Energy||RF Size|
|Register packing + Virtualization||1||1||1||0.43|
The table above summarizes the advantages of CORF, CORF++, and register packing (and register virtualization). All values normalized to the baseline GPU register file.
State Of Development
The design is fully prototyped in an architectural simulator (GPGPU-Sim). Some elements (e.g., hardware designs) have been further developed to evaluate complexity and energy efficiency.
Tech ID/UC Case
Name: Venkata Krishnamurty