Corf: Coalescing Operand Register File For Graphical Processing Units

Prof. Nael Abu-Ghazaleh and his research team have designed a novel, patent pending architecture for register coalescing to improve performance and energy efficiency – called CORF. Register coalescing combines multiple register reads into a singl…

Prof. Nael Abu-Ghazaleh and his research team have designed a novel, patent-pending architecture for register coalescing to improve performance and energy efficiency – called CORF. Register coalescing combines multiple registers reads into a single physical register read. The proposed design takes advantage of the coalescing opportunities through a combination of compiler-guided register allocation and coalescing-aware register organization. To maximize operand coalescing opportunities, CORF combines compiler-assisted register allocation with a reorganized RF – called CORF++.

CORF++ Overview

CORF++ Overview. At compile time, the alignment of the register through graph coloring algorithm to maximize coalescing opportunities.

Website:

https://techtransfer.universityofcalifornia.edu/NCD/32692.html?utm_source=AUTMGTP&utm_medium=webpage&utm_term=ncdid_32692&utm_campaign=TechWebsites

Advantages:

The benefits of their invention are:

  • Allows multiple operands to be read in a single cycle, overcoming port serialization.
  • The pressure on the RF is reduced potentially reducing register bank conflicts.
  • Combined savings of 17% in dynamic energy, reduction in number of reads by 23%, improvement in instruction per cycle/computation by 9%, and 52% of the leakage energy.
TechniqueIPCRegister readsRF Dynamic EnergyRF Size
Register packing1110.65
Register packing + Virtualization1110.43
CORF1.040.90.920.43
CORF++1.090.770.830.43

The table above summarizes the advantages of CORF, CORF++, and register packing (and register virtualization). All values normalized to the baseline GPU register file.

Additional Information:

State Of Development

The design is fully prototyped in an architectural simulator (GPGPU-Sim). Some elements (e.g., hardware designs) have been further developed to evaluate complexity and energy efficiency.

Related Materials

CORF: Coalescing Operand Register File for GPUs

Related Technologies

Tech ID/UC Case

32692/2019-123-0

Related Cases

2019-123-0, 2021-806-0

Contact Information:

Name: Venkata Krishnamurty

Title :

Department :

Email: venkata.krishnamurty@ucr.edu

Phone :

Address :